1. Field of the Invention
The present invention relates to a circuit device including a thin-film transistor (hereinafter abbreviated to a TFT). The present invention also relates to an active-matrix display apparatus having a circuit device including a TFT.
2. Description of the Related Art
In recent years, attention is being given to a light-emitting display apparatus using a light-emitting element as a next-generation display apparatus. In particular, a display apparatus using an organic electroluminescent (EL) element, which is a current-controlled light-emitting element whose emission luminance is controlled by a current, i.e., a so-called organic EL display apparatus, is known. One type of organic EL display apparatus is an active matrix display apparatus, which uses TFTs in a display region and a peripheral circuit and controls emission of light of organic EL elements by use of the TFTs. One known driving method used in the active-matrix display apparatus is a current programming technique of setting a current whose magnitude corresponds to image data in a pixel circuit disposed in a pixel and causing an organic EL element to emit light. The current corresponding to image data is output from a column control circuit. One example of the column control circuit is proposed in U.S. Pat. No. 7,126,565.
FIG. 12 illustrates the configuration of a column control circuit described in the above patent document. The column control circuit illustrated in FIG. 12 includes two voltage-to-current converters GMa and GMb. In operation, generally, while one of the two voltage-to-current converters GMa and GMb outputs current data, the other one samples an image signal and sets the current data. In this drawing, references M1 to M4, M6 to M10, and M12 represent n-type TFTs, references M5 and M11 represent p-type TFTs, references C1 to C4 represent capacitors, reference GND represents a first power source, and reference VCC represents a second power source. Reference Video represents an image signal, references SPa and SPb represent sampling signals, and references P1 to P6 represent control signals. The relationship between the gate sizes (width: W, length: L) in the transistors and that between the capacitances are that M1=M7, M2=M8, M3=M9, M4=M10, M5=M11, M6=M12, C1=C3, and C2=C4.
In FIG. 12, a case is described in which the channel characteristic of each TFT is specified, for example, the channel characteristic of M1 is the n type, and that of M5 is the p type. However, this is merely an example. If the relationship between the potential of the first power source GND and that of the second power source VCC is changed or the channel characteristics of the TFTs are inverted, the configuration may be changed as needed in response to the change or inversion.
For the sake of convenience of explanation in this specification, the gate electrode, source electrode, and drain electrode of a TFT are represented by the abbreviations /G, /S, and /D, respectively, and a signal and a signal line used for supplying the signal are represented without being distinguished.
FIG. 13 is a timing diagram for describing an operation of the column control circuit illustrated in FIG. 12. FIG. 13 illustrates an operation occurring in three horizontal scanning periods for an image signal, in other words, an operation corresponding to three columns (three horizontal scanning periods) for an organic EL display apparatus. Time t1 to time t7 (time t7 to time t13) corresponds to one horizontal scanning period.
The operation will be described below with reference to FIG. 13 while the attention is focused on the voltage-to-current converter GMa. The operation (1) to (6) described below is performed in sequence.    (1) Preliminary Charging (time t1 to time t2)
M3/G is charged by M5.    (2) Threshold Voltage Vth Resetting (time t2 to time t3)
M3/G is self-discharged such that the voltage approaches its threshold voltage Vth.    (3) Waiting for Sampling (time t4 to time t5)
The circuit waits in a state where the voltage of M3/G is adjacent to its threshold voltage Vth until a sampling signal SPa is input. At this time, the current of M3/D is substantially zero.    (4) Sampling (time t5 to time t6)
The sampling signal SPa for a corresponding column is generated, and the voltage of M3/G maintained adjacent to its threshold voltage Vth is changed by a transition voltage ΔV1 by an image signal level d1 with reference to a blanking level at this point in time.    (5) Waiting for Outputting (time t6 to time t7)
The circuit waits in a state where the voltage of M3/G set by sampling of the image signal is maintained. At this time, the current of M3/D driven by the voltage of M3/G is passed from M5.    (6) Current Outputting (time t7 to time t13)
The current of M3/D driven by the voltage of M3/G is output to Idata as current data.
After (6) (on and after time t13), the same operation is repeated from (1). The voltage-to-current converter GMb outputs a current (operation (6)) during the period from (1) to (5) (time t1 to time t7) and performs the operation (1) to (5) relating to setting of current data during the period (6) (time t7 to time t13).
As illustrated in the timing diagram of FIG. 13, this column control circuit operates with a plurality of control signals (P1 to P6) necessary for timing control. One example of the timing control is the control for causing the fall of a sampling signal SPa to occur after a fall of a control signal P1 in the period from time t3 to t4. This control is performed in order to cause M3/G to self-discharge stably by fixing a first terminal of the capacitor C1 at the potential of the image signal Video during resetting of the threshold voltage Vth. If the fall of the sampling signal SPa occurs in advance of the fall of the control signal P1, the voltage across the capacitor C1 is not changed even when the potential of M3/G is changed by self-discharging during that period. That is, the voltage of the capacitor C1 stored after the self-discharging is larger than the threshold voltage Vth of M3. To avoid this situation, it is necessary to delay the time of the fall of SPa from the time of the fall of P1. The same applies to the operation of P4 and SPb in the period from time t9 to t10 and the operation of P1 and SPa in the period from t15 to t16. No such limitation is imposed on the time of the rise of SPa and that of SPb. This is because, in the operation of preliminary charging (time t1 to time t2), if the rise of SPa is delayed from after that of P1 or P2, the preliminary charging into the capacitor C1 is not affected. One known method for delaying a signal from another signal is one that uses a delay circuit. U.S. Pat. No. 5,302,871 discloses a delay circuit in which a plurality of inverters, each including a plurality of transistors, are connected together. With the delay circuit, the time of the rise of a signal and the time of the fall of a signal are different at the input side and at the output side.
However, if a transistor, in particular, a TFT is used to control delay of a signal, because the characteristics vary, the driving characteristics of inverters or the values of capacitors vary. Because a control signal is input in parallel into column control circuits corresponding to the number of columns, the wiring for supplying the signal has a large time constant, so the signal is delayed. Therefore, when it is necessary to supply a plurality of control signals at slightly different times, a problem arises in which the times of the rises of the control signals or the times of the falls thereof may be inverted, and thus a desired operation may be unachievable.